An integrated circuit (IC) chip may become permanently damaged by peak voltages applied to the chip. For example, an oxide layer isolating a gate electrode of a metal-oxide semiconductor field effect transistor may be corrupted when receiving a spurious high-amplitude voltage spike. Such damage may be caused by excessive electrostatic discharge (ESD), when the gate electrode is connected to an external terminal or pin of the IC. ESD is a sudden and momentary electric current that flows between two objects at different electrical potentials caused by direct contact or induced by an electrostatic field. ESD may for example be caused by human handling of the chip. It can result from electrostatic electricity, for example caused by tribocharging or by electrostatic induction when an electrically charged object is placed near a conductive object isolated from ground. An ESD event may occur when this object comes into contact with a conductive path.
Due to size reduction in IC technologies, reduction of layer sizes has increased circuit sensitivity against ESD. Therefore, ESD protection has become an important focus of circuit development. However, applicability of active ESD protection structures having transistors is limited to a certain range of tolerable voltage amplitudes before damaging the protection circuits.
In U.S. Pat. No. 3,777,216, an avalanche injection input protection circuit is described. As shown in FIG. 1, a circuit 10 is provided for protecting an insulated gate field-effect transistor (IGFET) 12 from damage caused by high input voltages received through a pad 13. The protection circuit 10 comprises another IGFET 14 having its drain connected to the gate of the IGFET to be protected. The gate of the protection IGFET is connected to a reverse biased diode 16 connected to ground 18. In case of an ESD event, the protection IGFET 14 goes into an avalanche condition, where carrier injection from the drain to the gate occurs, the device switches to ON state, allowing carrier flow between drain and source, until the drain voltage drops below the avalanche maintenance value at which the charge built on the gate will be reduced through the diode 16, causing the protection device 14 to switch to OFF state again. The gate-drain and gate source Miller capacitances 20, 22 of the transistor 14 may provide a fast transient voltage divider enabling the protection transistor 14 in case of an ESD event. The diode is a resistive leakage path for discharging the gate capacity of the protection transistor 14, discharging slow enough for ESD events, fast enough for normal operation of the main circuit to be protected.
In US RE38,319 E, a dual-node capacitor coupled MOSFET for improving ESD performance is presented, allowing for ESD protection for a comparably low voltage range. A capacitor is connected between the gate of a protection circuit NMOS device and a pad, and the device is back biased via a resistor.
In U.S. Pat. No. 4,423,431, a semiconductor integrated circuit device providing a protection circuit is shown. The protection circuit consists of a protection transistor having a drain connected to a gate of a transistor to be protected. If an excessively high voltage is applied to the input gate, the protection transistor is turned ON to cause an electric charge to be passed to ground.